1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for forming a contact portion between a semiconductor substrate (high impurity concentration layer) and a wiring layer or between upper and lower wiring layers in miniaturized semiconductor integrated circuit devices.
2. Description of the Related Art
In general, in order to form a contact portion between a semiconductor substrate (high impurity concentration layer) and a wiring layer in semiconductor integrated circuit devices, the manufacturing steps shown in FIGS. 1A to 1C are used. First, element isolation region 12 is formed on the main surface of silicon substrate 11, by means of the element isolation technique as shown in FIG. 1A. Then, an impurity is doped into silicon substrate 11 by way of an ion implantation technique, with element isolation region 12 used as a mask, to form high impurity concentration region 13. An N-type impurity (donor) or a P-type impurity (acceptor) is used as the impurity for forming high impurity concentration region 13 when silicon substrate 11 is of P-type or N-type, respectively. Next, after CVD-SiO.sub.2 film 14 is formed on the entire surface of the resultant structure, contact hole 15 is formed in CVD-SiO.sub.2 film 14 by using a photolithographic method. Thus, a semiconductor structure as shown in FIG. 1B is obtained. Then, an Al--Si layer is formed on the entire surface of the semiconductor structure by using a sputtering method, and wiring layer 16 is formed by using the photolithographic method. Further, passivation film 17 is formed on the entire surface of the semiconductor structure, to complete the wiring process, thus forming a semiconductor structure as shown in FIG. 1C.
In the method of forming the contact portions as described above, various problems relating to the electrical characteristics and reliability of the contact portion may occur, as are described below with reference to items (1) to (3).
(1) The contact resistance increases in inverse proportion to the area of the contact in the case where the contact is made small in size. When wiring layer 16 is formed of Al--Si as described above, Si atoms in the Al--Si will be precipitated at the interface between silicon substrate 11 and wiring layer 16 during the heat treatment process (at about 450.degree. C.), which is effected to remove the process damage induced by various process steps, thus reducing the effective area of the contact. Process damages will occur when plasma and reactive ion etching are done or an impurity is ion-implanted to form high impurity concentration layer 13 or when an impurity is ion-implanted to form semiconductor elements (not shown) at the peripheral circuit. Therefore, it is necessary that a heat treatment process be effected in order to reduces damage such as interface state. This heat treatment, however, results in a further increase in the contact resistance. An increase in the contact resistance becomes conspicuous when the contact area is made smaller than 1 .mu.m.sup.2. Further, aluminum in wiring layer 16 may sometimes absorbs Si atoms in silicon substrate 11, thus breaking the PN junction between substrate 11 and impurity layer 13.
(2) When the contact is made small in size, the step coverage of wiring layer (Al--Si) 16 becomes poor and the flatness of wiring layer 16 at the contact portion becomes extremely low, thus leaving the wiring layer easily breakable. As is shown in FIG. 1C, wiring layer 16 is made thin on side wall portions 16A and 16B of contact hole 15. The thin film portion of wiring layer 16 may cause open failure and electromigration due to an increase in the current density, lowering the reliability of the contact portion. Further, the poor step coverage of the wiring layer may cause a cavity in contact hole 15 at the time of formation of wiring layer 16. In these circumstances, when an insulation film is formed on wiring layer 16 and a second wiring layer is formed on the insulation film, insulation between the two wiring layers may become deteriorate. In other words, if a cavity is formed as described above, cracks may easily occur in the insulation film between wiring layer 16 and the second wiring layer due to stress caused by high temperature or the like. In addition, moisture trapped in the cavity may corrode wiring layer 16, rendering the wiring defective.
(3) With the high integration of semiconductor devices, the thickness of the entire wiring layer 16 becomes small. However, since a reduction in the thickness of the wiring layer increases the current density, this results in the wiring layer being more susceptible to stress- and electro-migration, remarked low reliability of the contact portion.
The same problems as described above may occur in the case where a contact portion for a wiring layer and an upper wiring layer formed over the wiring layer is formed. However, in this case, it is free from the problem where Si atoms are precipitated at the interface between the silicon substrate and wiring layer, reducing the effective contact area, and where aluminum in the wiring layer absorbs Si atoms in the silicon substrate, thereby causing the PN junction to break.